Heretofore, an LDMOS (Laterally Diffused MOSFET) is used as a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Usually, a film thickness of the gate insulating film of the LDMOS is about 12.5 nm in order to reduce an ON resistance, and therefore, a gate voltage is limited to not more than 5 V. Consequently, when the power-supply voltage of this LDMOS is higher than 5 V, if the power-supply voltage is directly used as the gate voltage of the LDMOS, the gate insulating film is likely to be broken down. For this reason, when the power-supply voltage is higher than 5 V, a circuit for generating the gate voltage of the LDMOS is required, and the circuit becomes complicated. As a result, there arise problems that the semiconductor device is increased in size and increased in cost.
To enable the gate insulating film to be resistant to high voltage, it is considered to make the film thickness thereof thick. However, since current capability of the MOSFET is proportional to the capacity of the gate insulating film, and the capacity of the gate insulating film is inversely proportional to the film thickness of the gate insulating film, when the gate insulating film is made thick, the current capability is reduced inversely proportional thereto, and the ON resistance increases. Further, a threshold voltage also increases. To reduce the threshold voltage, when the impurity concentration of a channel is reduced, a short channel effect becomes remarkable. To remedy the situation, when a channel length is made long, the ON resistance further increases. To compensate for the increase of the ON resistance, when an element area is increased, the semiconductor device is further increased in size, and also increased in cost.